This invention relates to a device for limiting and making uniform the current through microtips of a cathodic structure for flat panel displays (FPD) of the field emission type (FED). More in particular, the process of the invention relates to the formation of microtips of a refractory metal by sputtering in preformed wells and removing the deposition overstructure.
The continuous evolution towards portable electronic products such as laptop computers, personal organizers, pocket TVs and electronics games, has created an enormous market for monochromatic or color display screens of small dimensions and reduced thickness, having a light weight and a low dissipation. The first two requirements of small dimensions and reduced thickness cannot be met by conventional cathode ray tubes (CRT). For this reason, among the emerging technologies, in addition to those related to liquid-crystal-displays (LCD), flat panel field emission display technology has been receiving increased attention by the industry.
Over the past few decades, remarkable research and development work has been carried out on field emission displays (FED) employing a cathode in the form of a flat panel provided with a dense population of emitting microtips co-operating with a grid-like extractor essentially coplanar to the apexes of the microtips. The cathode-grid extractor structure is a source of electrons that are accelerable in a space, evacuated for ensuring an adequate mean free-path, towards a collector (anode) constituted by a thin and transparent conductor film upon which are placed luminescent phosphors excited by the impinging electrons. Emission of electrons is modulately excitable pixel by pixel through a matrix of columns and rows, constituted by parallel strips of the population of microtips and parallel strips of the grid-like extractor, respectively. The fundamental structure of these display systems, the main problems related to the fabrication technology, including reliability, durability, and those concerning the peculiar way of exciting individual pixels of the display system, and the various proposed solutions to these problems, are discussed and described in a wealth of publications on these topics. Among the pertinent literature, the following publications may be cited and are hereby incorporated by reference:
U.S. Pat. No. 5,391,259; Cathey, et al. PA0 U.S. Pat. No. 5,387,844; Browning PA0 U.S. Pat. No. 5,357,172; Lee, et al. PA0 U.S. Pat. No. 5,210,472; Casper, et al. PA0 U.S. Pat. No. 5,194,780; Meyer PA0 U.S. Pat. No. 5,064,396; Spindt PA0 U.S. Pat. No. 4,940,916; Borel, et al. PA0 U.S. Pat. No. 4,857,161; Borel, et al. PA0 U.S. Pat. No. 3,875,442; Wasa, et al. PA0 U.S. Pat. No. 3,812,559; Spindt, et al. PA0 U.S. Pat. No. 3,755,704; Spindt, et al. PA0 U.S. Pat. No. 3,655,241; Spindt, et al.
"Beyond AMLCDs: Field emission displays?", K. Derbyshire, Solid State Technology, November 1994; PA1 "The state of the Display", F. Dawson, Digital Media, February-March 1994; PA1 "Competitive Display Technologies", 1993, Stanford Resources, Inc.; PA1 "Field-Emission Display Resolution", W. D. Kesling, et al., University of California, SID 93 DIGEST 599-602; PA1 "Phosphors For Full-Color Microtips Fluorescent Displays", F. Levy, R. Meyer, LETI--DOFT--SCMM, IEEE 1991, pages 20-23; PA1 "Diamond-based field emission flat panel displays", N. Kumar, H. Schmidt, Solid State Technology, May 1995, pages 71-74; PA1 "Electron Field Emission from Amorphic Diamond Thin Films", Chenggang Xle, et al., Microelectronics and Computer Technology Corporation, Austin, Tex.; University of Texas and Dallas, Richardson, Tex.; SI Diamond Technology, Inc., Houston, Tex.; PA1 "Field Emission Displays Based on Diamond Thin Films", Natin Kumar, et al:, Microelectronics and Computer Technology Corporation, Austin, Tex.; Elliot Schlam Associates, Wayside, N.J.; SI Diamond Technology, Inc., Houston, Tex.; PA1 "U.S. Display Industry on the Edge", Ken Werner, Contributing Editor, IEEE Spectrum, May 1995; PA1 "FEDs: The sound of silence in Japan", OEM Magazine, April 1995, pages 49, 51; PA1 "New Structure Si Field Emitter Arrays with low Operation Voltage", K. Koga, et al., 2.1.1, IEDM 94-23. PA1 low dissipation; PA1 same color quality of traditional CRTs; and PA1 visibility from any viewing angle.
The major advantages of FEDs compared to modern LCDs include:
FED technology has been developed on the basic teachings contained in U.S. Pat. Nos. 3,665,241; 3,755,704 and 3,812,559 of C. A. Spindt and in U.S. Pat. No. 3,875,442 of K. Wasa, et al. FED technology connects back to conventional CRT technology, in the sense that light emission occurs because of the excitation of the phosphors deposited on a metallized glass screen, which is bombarded by electrons accelerated in an evacuated space. The main difference is the manner in which electrons are emitted and the image is scanned.
A concise but thorough account of the state of modern FED technology is included in a publication entitled "Competitive Display Technologies--Flat Information Displays" by Stanford Resources. Inc., Chapter B "Cold Cathode Field Emission Displays". A schematic illustration contained in that publication which gives a comparison between a conventional CRT display and a FED (or FED array) is reproduced in FIG. 1. In a traditional CRT, a single cathode 100 in the form of an electron gun 110 (or a single cathode for each color) is provided and magnetic or electrostatic yokes 120 deflect the electron beam for repeatedly scanning the screen 130, whereas in a FED, the emitting cathode 150 is constituted by a dense population of emission sites 160 distributed more or less uniformly over the display area. Each site is constituted by a microtip 170 electrically excitable by means of a grid-like extractor 180. This flat cathode-grid assembly is set parallel to the screen 190, at a relatively short distance from it. The scanning by pixel of the display is performed by sequentially exciting individually addressable groups of microtips 170 by biasing them with an adequate combination of grids and cathode voltages.
As shown in FIG. 2, a certain area of the cathode-grid structure containing a plurality of microtips and corresponding to a pixel of the display is sequentially addressed through a driving matrix organized in rows and columns (in the form of sequentially biasable strips, into which the cathode is electrically divided and of sequentially biasable strips into which the grid extractor is electrically divided, respectively).
A typical scheme for driving a pixel of the cathodic structure of a FED is shown in FIG. 3. This figure illustrates the driving scheme of a fragment of nine adjacent pixels through a combination of the sequential row biasing pulses for the three rows R1, R2, R3, relative to a certain bias configuration of the three columns C1, C2 and C3.
A typical cross-sectional view of a FED structure is shown in FIG. 4. The microtip cathode plate generally comprises a substrate of an isolating material such as glass, ceramic, or silicon 400, onto which is deposited a low resistivity conductor layer 410, for example, a film of aluminum, niobium, nickel, or a metal alloy, eventually interposing an adhesion layer of, for example, silicon 420 between the substrate 400 and the conductor layer 410.
The conductor layer 410 is photolithographically patterned into an array of parallel strips each constituting a column of a driving matrix of the display. A dielectric layer 430, for example, an oxide, is deposited over the patterned conductor layer 410. Another conductor layer 440, from which the grid extractor will be patterned, is deposited over the dielectric layer 430.
The grid structure is eventually defined in parallel strips, normal to the cathode parallel strips 410. According to a known technique, micro-apertures or wells that reach down to the surface of the under-lying patterned conductor layer 410 are defined and cut through the grid conductor layer 440 and through the underlying dielectric layer 430. Onto the surface of the conductor layer exposed at the bottom of the "wells", are fabricated microtips 450 that constitute the many sites of emission of electrons.
On the inner face of a glass faceplate 460 of the display is deposited a transparent thin conducting film 470, for example, a mixed oxide of indium and tin upon which is deposited a layer of phosphors 480 (monochromatic phosphor or color phosphors) excitable by the electrons accelerated toward the conducting layer 470 and acting as a collector of the electrons emitted by the microtips 450. Emission is stimulated by the electric field produced by suitably biasing the grid conductor 440 and the cathode tips 450.
In order to improve color resolution, the realization of a "switched" anodic (collector) structure for separately biasing adjacent strips, each covered with a phosphor of a different basic color, has been suggested in a publication entitled: "Phosphors For Full-Color Microtips Fluorescent Displays" by F. Levy and R. Mayer, LETI-DOFT-SCMM, Grenoble-Cedex-France.
According to a known process for fabricating the cathodic structure of a FED, after completing the formation of the grid of niobium, or of any other self-passivating metal, and employing the etching solutions normally used in the fabricating process, a lift-off layer is deposited on the grid. This lift-off layer is generally constituted by a metal that is easily and selectively wet-etchable through its exposed edges so to allow the removal (lift-off) of the cone deposition overstructure. This deposition process is carried out by sputtering at a normal incidence with the panel surface, a metal (usually a refractory metal such as molybdenum) that is also capable of resisting the etch conditions during the lift-off to form deposition cones within the wells that have been formed through the grid openings layer and an underlying dielectric layer.
The bottom of the deposition wells of the cones is constituted by a substantially conductive layer and, more preferably, by a special conductive layer purposely having a high resistivity, superimposed to the highly conductive material of the selectable cathodic conductors or strips.
Prevention of lift-off material deposition inside the wells is of paramount importance.
At present, this critical requisite of the fabrication process is fulfilled by using deposition techniques of the lift-off layer that avert deposition onto the bottom of the wells. Commonly, a lift-off layer of nickel is deposited by vacuum evaporation, while maintaining an extremely small angle of incidence of the impinging nickel (i.e. at grazing angle). Of course, the panel under fabrication must be rotated around its own axis while maintaining a minimum angle of incidence with respect to the impinging flow so as to obtain a deposition of uniform thickness. This requires the presence of complex and inevitably encumbering organs for rotating the panel in the vacuum deposition chamber, considering that the panels can reach dimensions of 27.times.36 cm. All of this increases the costs of fabrication of these panels. The criticality of this stage of the fabrication process also has negative repercussions on production yields.
Confronted with this state of the art technique, an improved fabricating procedure that substantially obviates the above-mentioned critical aspects of well known processes embodies the present invention. The process of preferred embodiments of the invention does not require the use of special grazing-angle-deposition devices, and reduces the manufacturing costs while improving the yield.
Basically, the preferred process of the invention, different from well known processes, does not contemplate a complete pre-definition of the grid structure, rather a corrosion-resisting metallic material, from which the grid structure will be defined, is deposited onto a matrix layer. In addition, a layer of a lift-off material that can be easily and selectively etched is deposited prior to forming the grid apertures and the corresponding wells, inside which the cathodic microtips will be eventually formed.
The lift-off material can be the same masking resist or, if of another type of material, such a layer is contextually defined with the grid matrix layer and the underlying isolation dielectric layer during the etching that is performed to form the grid apertures angle and the corresponding wells.
According to a first embodiment of the invention, a lift-off layer constituted by a thin layer of nickel or of another easily dissolvable metal can be used. The lift-off layer can be deposited by vacuum evaporation or sputtering at a normal incidence directly onto the surface of a grid metal matrix (still unpatterned) layer whose thickness is generally greater than the thickness of the lift-off layer. The grid matrix layer can be, for example, niobium, tungsten, chromium, or tantalum, or alloys or stacked layers thereof deposited by vacuum evaporation, or it can be an adequately doped polycrystalline or amorphous silicon.
Parallel strips orthogonal to the cathodic conductors can optionally be predefined before depositing of the nickel or similar lift-off material. Subsequently, circular apertures with a diameter of about 1.0-1.5 micrometers, densely and uniformly distributed over the surface of each strip, are thereafter defined through a masking step.
The etching of the stack through the apertures of the resist mask, that comprises the thin lift-off layer of nickel or similar metal, the grid matrix layer of corrosion resistant metal, and the underlying dielectric layer, typically of silicon oxide, can be conducted in different phases.
The known difficulty of dry-etching (i.e. plasma etching) of the nickel, consisting of the formation of non-volatile nickel compounds is overcome by resorting to an ion-milling technique or the like. The etching of the thin top layer of nickel or similar metal through the apertures of the mask can be carried out by a sputter etch with Argon ions. Nickel is the preferred metal due to the fact that it shows a relatively high yield to sputtering.
The possibility of carrying out a "sputter etch" in an Argon plasma is generally offered by standard deposition plasma reactors. This feature is normally available for allowing the removal of possible superficial (native) oxide layers before starting the vacuum deposition. However, this feature may be easily included in other common apparatuses, such as in the same R.I.E. reactor that is used for eventually etching the grid matrix layer and the underlying isolating oxide. For example, the R.I.E. Precision 5000 or Centura models, both by Applied Materials Corporation, can be easily equipped to permit the carrying out of an Argon sputter etch.
In the above-identified R.I.E. etcher, a preliminary Argon sputter etch phase can be carried out with a power of 300 W (corresponding to a plasma voltage of about 500V). The removal of a thin lift-off layer of nickel, whose thickness is typically on the order of 15-20 nanometers (nm), would require a treatment of about two to three minutes. In a case such as this, it is convenient to use, as a grid matrix material, a doped polycrystalline or amorphous silicon layer or a tungsten layer, because both of these materials are characterized by a sputter yield markedly lower than that of nickel. Therefore, they provide for advantageous conditions for implementing an automatic stop of the sputter etching of the nickel layer, according to well known techniques.
The anisotropic plasma etching of the grid matrix layer (for example, polycrystalline silicon, tungsten, or niobium) and the subsequent etching of the underlying oxide or similar dielectric layer that isolates the cathodic structure from the grid, can be carried out in sequence by the same etcher, using different chambers thereof, with different plasma compositions, specifically suited for the progression of the etching through the different materials that make up the "stack" to be etched, until the surface of the high resistivity layer (for example, doped polycrystalline silicon), of the cathodic structure is exposed.
Alternatively, the lift-off layer of nickel can be preliminarily etched through the masking apertures, by carrying out a wet-etching step in an appropriate etching solution, for example, a solution of hydrochloric acid, in a controlled manner so as to avoid overetching the nickel layer underneath the edges of the resist mask. The two types of etchings can be alternated in order to ensure a complete removal of the nickel from the unmasked areas without undercutting the nickel under the mask.
After completing the etching through the stack and removing the resist mask, a suitable refractory and etch-resistant metal, for example molybdenum, is deposited by "vertical" or "quasi-vertical" sputtering, according to a common technique. This phase of construction of the microtips comprises a plurality of steps. For example, it can comprise a first stage during which a thin film (in the order of some hundreds of Angstroms) of an adhesion (for example, chromium, tantalum or similar material) material having a relatively good crystallographic affinity with the base material, typically a high resistivity doped polycrystalline silicon layer, is deposited. Obviously, several layers of different materials can be deposited prior to a final deposition step.
During the last deposition step, the shielding effect of the walls of the preformed wells determines the formation of cones of deposition inside the wells, whose sharp vertex approximately reaches the level of the grid before an eventual occlusion of the deposition window in the deposited overstructure that grows over the lift-off layer.
Through an electrochemical etching of the lift-off layer, left exposed at the rims of the wells, the deposited overstructure of molybdenum is removed (lifted-off), thus leaving the deposition cones inside the wells cut through the isolating dielectric layer in correspondence with the grid openings.
The dissolution of the lift-off layer is accelerated by anodically biasing the nickel in an acid bath, commonly with a pH ranging between 2.5 and 3.
The lift-off etching of the nickel layer can be performed in an aqueous bath containing ammonium chloride, nickel chloride and boric acid and using a biasing counterelectrode (cathode) of nickel. The anodic biasing of the lift-off nickel layer can be arranged by contacting the front of the panel, that is, the deposited conductive overstructure. In this lift-off step of the deposition overstructure of molybdenum or of a stack of superimposed etch-resistant-metals through an anodic dissolution of the underlying nickel layer, the FED panel preformed cathodic structure is suitably left floating to prevent any possibility of corrosion of metallic components of the cathodic structure, and in particular, of the microtips themselves. Moreover, the relative corrosion resistance of the molybdenum tips and of the tungsten and/or niobium grid, is also ensured by a lower electronegativity of these metals as compared to that of nickel, and by the ability of these so-called valve metals to passivate themselves under anodic polarization conditions, thus impeding any further flow of corrosion current.
Similar wet etch resistance properties are also possessed by the polycrystalline silicon of the bottom layer of the wells onto which the cones of deposition are grown. By contrast, the end edges of the cathodic conductors, when they are realized with an easily corrodible metal such as nickel, must be appropriately protected during the lift-off wet-etching step. Obviously, if the cathodic conductors are made of a non-corrodible material, such as mixed indium and tin oxides, these precautions will not be necessary.
According to a preferred embodiment of the invention, and prior to depositing a thin lift-off layer (for example, nickel), the grid matrix layer (for instance, a doped polycrystalline or amorphous silicon, tungsten, chromium or niobium), can be patterned in parallel strips, orthogonally oriented to the cathodic conductors through a first masking and etching step. In this first patterning step of the grid structure in the form of a plurality of parallel strips, the etching is not continued through the underlying dielectric.
By performing such a preliminary patterning in parallel strips of the grid structure, prior to defining the wells into which the cones will be formed, "steps" are produced that interrupt the continuity of the grid matrix layer along a direction orthogonal to the orientation of the strips into which the grid is subdivided. This advantageously increases the number and extension of the exposed edges of the lift-off layer, which has a thickness lower than the patterned strips of the grid matrix layer, through which electrochemical etching will occur. In this way, the lift-off etching can proceed more rapidly and uniformly throughout the panel.
According to an alternative embodiment, the lift-off layer may be constituted by the residual layer of masking resist employed for defining the grid apertures during the etching of the grid conductor layer and of the underlying dielectric.
According to this embodiment, a first patterning step using an appropriate resist and a successive anisotropic etching, for example by R.I.E., defines circular apertures of a diameter ranging approximately between 1.0-1.5 micrometers, densely distributed over the surface of the grid matrix layer. These circular apertures (holes or wells) are formed through each grid strip and through the underlying dielectric layer, typically silicon oxide, until reaching the surface of a high resistivity layer, for example, doped polycrystalline silicon, for limiting the emission current through the microtips.
Without removing the residual resist layer of the mask, a suitable etch-resistant and refractory metal such as molybdenum is deposited via "vertical" or "quasi vertical" sputtering, according to a standard technique. The shielding effect of the walls of the preformed wells determines the growth of deposition cones in the wells whose sharp-pointed vertexes reach approximately the level of the grid layer before an eventual occlusion of the corresponding deposition window through the overstructure that grows above the resist layer.
By using a resist particularly resistant to high temperature and eventually hardened after development by exposure to UV radiation and/or heat (for example, the same type of resist commonly used for shielding drain and source implantations for defining the grid apertures and the corresponding wells), the resist mask layer that remains at the completion of the anisotropic plasma etching of the grid apertures and of the corresponding wells can be used as a lift-off layer for removing the deposition overstructure of the conductive cones grown by sputtering.
The deposition overstructure is lifted-off by etching this residual layer of masking resist in an oxygen plasma, which can precede or follow a wet-softening of the resist with, for example, organic strippers, such as EKC265, that are composed of chemically activated organic solvents having a medium boiling temperature.
The definition of the grid into parallel strips orthogonal to the cathodic conductors can take place in a quite customary manner, through a distinct masking step.
In either one of the above described embodiments of the invention, carrying out depositions at a "grazing" angle of incidence requiring the use of special devices to ensure an acceptable uniformity of the deposit is avoided. Moreover, any accidental deposition of lift-off material inside (on the bottom) of preformed wells is positively prevented, thus eliminating the consequent critical aspects of the known processes.